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TDA9115
LOW-COST I2C CONTROLLED DEFLECTION PROCESSOR FOR MULTISYNC MONITOR
FEATURES General 2 s I C-BUS-CONTROLLED DEFLECTION PROCESSOR DEDICATED FOR LOW-END CRT MONITORS s SINGLE SUPPLY VOLTAGE 12V s VERY LOW JITTER s DC/DC CONVERTER CONTROLLER s ADVANCED EW DRIVE s AUTOMATIC MULTISTANDARD SYNCHRONIZATION s DYNAMIC CORRECTION WAVEFORM OUTPUT s X-RAY PROTECTION AND SOFT-START & STOP ON HORIZONTAL AND DC/DC DRIVE OUTPUTS Horizontal section s 150 kHz maximum frequency s Corrections of geometric asymmetry: Pin cushion asymmetry, Parallelogram s Tracking of asymmetry corrections with vertical size and position s Horizontal moire cancellation output Vertical section s 200 Hz maximum frequency s Vertical ramp for DC-coupled output stage with adjustments of: C-correction, S-correction for super-flat CRT, Vertical size, Vertical position s Vertical moire cancellation through vertical ramp waveform s Compensation of vertical breathing with EHT variation EW section s Symmetrical geometry corrections: Pin cushion, Keystone s Horizontal size adjustment s Tracking of EW waveform with Vertical size and position and adaptation to frequency s Compensation of horizontal breathing through EW waveform Dynamic correction section s Vertical dynamic correction waveform output for dynamic corrections like focus, brightness uniformity, ... s Fixed on screen by means of tracking system DC/DC controller section s Step-up and step-down conversion modes s External sawtooth configuration s Synchronization on hor. frequency with phase selection s Selectable polarity of drive signal DESCRIPTION The TDA9115 is a monolithic integrated circuit assembled in a 32-pin shrink dual-in-line plastic package. This IC controls all the functions related to horizontal and vertical deflection in multimode or multi-frequency computer display monitors. The device only requires very few external components. Combined with other ST components dedicated for CRT monitors (microcontroller, video preamplifier, video amplifier, OSD controller) the TDA9115 allows fully I2C bus-controlled computer display monitors to be built with a reduced number of external components.
SHRINK 32 (Plastic Package) ORDER CODE: TDA9115
Version 4.0
August 2001 1/45
1
TABLE OF CONTENTS
-PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 -PIN FUNCTION REFERENCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 -QUICK REFERENCE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 -ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 -ELECTRICAL PARAMETERS AND OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . 8 6.1 THERMAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.2 SUPPLY AND REFERENCE VOLTAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.3 SYNCHRONIZATION INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.6 EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6.7 DYNAMIC CORRECTION OUTPUTS SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.8 DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.9 MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7 -TYPICAL OUTPUT WAVEFORMS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2 8 -I C BUS CONTROL REGISTER MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9 -OPERATING DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1 SUPPLY AND CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.1 Power supply and voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.1.2 I2C Bus Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2 SYNC. PROCESSOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.1 Synchronization signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 9.2.2 Automatic sync. selection mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3 HORIZONTAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.2 PLL1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9.3.3 Voltage controlled oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3.4 PLL2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3.5 Dynamic PLL2 phase control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.3.6 Output section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3.7 Soft-start and soft-stop on H-drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.3.8 Horizontal moire cancellation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 9.4 VERTICAL SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 9.4.2 Vertical moire . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.5 EW DRIVE SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 9.6 DYNAMIC CORRECTION OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.6.1 Vertical Dynamic Correction output VDyCor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.7 DC/DC CONTROLLER SECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9.8 MISCELLANEOUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.1 Safety functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.2 Soft start and soft stop functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.3 X-ray protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.8.4 Composite output HLckVBk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10 -INTERNAL SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2 11 -PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12 -GLOSSARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 1 2 3 4 5 6
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TDA9115
1 - PIN CONFIGURATION
H/HVSyn VSyn HLckVBk HOscF HPLL2C CO HGND RO HPLL1F HPosF HMoire HFly RefOut BComp BRegIn BISense
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VDyCor SDA SCL Vcc BOut GND HOut XRay EWOut VOut VCap VGND VAGCCap VOscF VEHTIn HEHTIn
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4/45
HGND
7
2 - BLOCK DIAGRAM
TDA9115
HPosF
10
HPLL1F
9
R0
8
C0 HOscF
6 4
HFly
12
HPLL2C
5
H/HVSyn
1
H-sync detection Polarity handling
Phase/frequency comparator
Horizontal position
Horizontal VCO
Phase comparator Phase shifter H duty controller
Pin cushion asymm. Parallelogram
H-drive buffer
26
HOut
Lock detection HLckVBk
3
PLL1
H-moire controller
H-moire amplitude
Safety processor
25
XRay
V-blank H-lock
28
BOut BISense BRegIn BComp
PLL2
SDA SCL
31 30
I2C Bus interface
:
B+ DC/DC converter controller
16
15
I2C Bus registers
Functions controlled via I2C Bus
14
Vcc
29
Supply supervision Reference generation
Internal ref.
RefOut
13
V-sync extraction & detection
V-dynamic correction (focus, bright.)
VDyCor amplitude
11
Geometry tracking
HMoire
GND
27
V-sync detection Input selection Polarity handling
Vertical oscillator with AGC
S-correction C-correction
V-ramp control Tracking EHT
Vertical size Vertical position Vertical moire
EW generator
H size Pin cushion Keystone
24
EWOut
2
21
19
20
22
32
23
18
17
TDA9115
VSyn
VGND
VOscF VCap VDyCor VAGCCap
VOut
VEHTIn
HEHTIn
TDA9115
3 - PIN FUNCTION REFERENCE
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name H/HVSyn VSyn HLckVBk HOscF HPLL2C CO HGND RO HPLL1F HPosF HMoire HFly RefOut BComp BRegIn BISense HEHTIn VEHTIn VOscF VAGCCap VGND VCap VOut EWOut XRay HOut GND BOut Vcc SCL SDA VDyCor TTL compatible Vertical Sync. input Horizontal PLL1 Lock detection and Vertical early Blanking composite output High Horizontal Oscillator sawtooth threshold level Filter input Horizontal PLL2 loop Capacitive filter input Horizontal Oscillator Capacitor input Horizontal section GrouND Horizontal Oscillator Resistor input Horizontal PLL1 loop Filter input Horizontal Position Filter and soft-start time constant capacitor input Horizontal Moire cancellation output Horizontal Flyback input Reference voltage Output B+ DC/DC error amplifier (Comparator) output Regulation feedback Input of the B+ DC/DC converter controller B+ DC/DC converter current (I) Sense input Input for compensation of Horizontal amplitude versus EHT variation Input for compensation of Vertical amplitude versus EHT variation Vertical Oscillator sawtooth low threshold Filter (capacitor to be connected to VGND) Input for storage Capacitor for Automatic Gain Control loop in Vertical oscillator Vertical section GrouND Vertical sawtooth generator Capacitor Vertical deflection drive Output for a DC-coupled output stage E/W Output X-Ray protection input Horizontal drive Output Main GrouND B+ DC/DC converter controller Output Supply voltage I2C bus Serial CLock Input I2C bus Serial DAta input/output Vertical Dynamic Correction output Function TTL compatible Horizontal / Horizontal and Vertical Sync. input
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TDA9115
4 - QUICK REFERENCE DATA
Characteristic General Package Supply voltage Supply current Application category Means of control/Maximum clock frequency EW drive DC/DC convertor controller Horizontal section Frequency range Autosync frequency ratio (can be enlarged in application) Positive/Negative polarity of horizontal sync signal/Automatic adaptation Duty cycle of the drive signal Position adjustment range with respect to H period Soft start/Soft stop feature Hardware/Software PLL lock indication Parallelogram Pin cushion asymmetry correction (also called Side pin balance) Top/Bottom/Common corner asymmetry correction Tracking of asymmetry corrections with vertical size & position Horizontal moire cancellation (ext.) for Combined/Separated architecture Vertical section Frequency range Autosync frequency range (150nF at VCap and 470nF at VAGCCap) Positive/Negative polarity of vertical sync signal/Automatic adaptation S-correction/C-correction/Super-flat tube characteristic Vertical size/Vertical position adjustment Vertical moire cancellation (internal) Vertical breathing compensation EW section Pin cushion correction Keystone correction Top/Bottom/Common corner correction Horizontal size adjustment Tracking of EW waveform with Frequency/Vertical size & position Breathing compensation on EW waveform Dynamic correction section (dyn. focus, dyn. brightness,...) Vertical dynamic correction output VDyCor Horizontal dynamic correction output Composite HV dynamic correction output Tracking of horizontal waveform with Horizontal size/EHT Tracking of vertical waveform with V. size & position DC/DC controller section Step-up/Step-down conversion mode Internal/External sawtooth configuration Bus-controlled output voltage Soft start/Soft stop feature Positive(N-MOS)/Negative(P-MOS) polarity of BOut signal Value SDIP 32 12 55 Low-end I2C Bus/400 Yes Yes 15 to 150 4.28 Yes/Yes/Yes 48 11 Yes/Yes Yes/No Yes Yes No/No/No Yes Yes/Yes 35 to 200 50 to 180 Yes/Yes/Yes Yes/Yes/Yes Yes/Yes Yes Yes Yes Yes No/No/No Yes Yes/Yes Yes Yes No No No/No Yes Yes/Yes No/Yes No Yes/Yes Yes/Yes Unit
V mA kHz
kHz
% %
Hz Hz
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TDA9115
5 - ABSOLUTE MAXIMUM RATINGS
All voltages are given with respect to ground. Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive.
Symbol VCC Supply voltage (pin Vcc) Pins HEHTIn, VEHTIn, XRay, HOut, BOut Pins H/HVSyn, VSyn, SCL, SDA Pins HLckVBk, CO, RO, HPLL1F, HPosF, HMoire, BRegIn, BISense, VAGCCap, VCap, VDyCor, HOscF, VOscF Pin HPLL2C Pin HFly ESD susceptibility (human body model: discharge of 100pF through 1.5k) Storage temperature Junction temperature Parameter Value Min -0.4 -0.4 -0.4 -0.4 -0.4 -0.4 -2000 -40 Max 13.5 VCC 5.5 VRefO VRefO/2 VRefO 2000 150 150 Unit V V V V V V V C C
V(pin)
VESD Tstg Tj
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TDA9115
6 - ELECTRICAL PARAMETERS AND OPERATING CONDITIONS
Medium (middle) value of an I2C Bus control or adjustment register composed of bits D0, D1,...,Dn is the one having Dn at "1" and all other bits at "0". Minimum value is the one with all bits at 0, maximum value is the one with all at "1". Currents flowing from the device (sourced) are signed negative. Currents flowing to the device are signed positive. TH is period of horizontal deflection.
6.1 THERMAL DATA
Symbol Tamb R th(j-a) Parameter Operating ambient temperature Junction-ambience thermal resistance 0 65 Value 70 Unit C C/W
6.2 SUPPLY AND REFERENCE VOLTAGES
Tamb = 25C
Symbol VCC ICC VRefO IRefO Parameter Supply voltage at Vcc pin Supply current to Vcc pin Reference output voltage at RefOut pin Current sourced by RefOut output VCC = 12V VCC = 12V, IRefO= -2mA 7.4 -5 Test Condit ions Min. 10.8 Value Typ. 12 55 8 8.6 0 Max. 13.2 V mA V mA Units
6.3 SYNCHRONIZATION INPUTS
Vcc = 12V, Tamb = 25C
Symbol VLoH/HVSyn VHiH/HVSyn VLoVSyn V HiVSyn R PdSyn tPulseHSyn tPulseHSyn/T H tPulseVSyn tPulseVSyn/T V textrV/T H tHPolDet Parameter LOW level voltage on H/HVSyn HIGH level voltage on H/HVSyn LOW level voltage on VSyn HIGH level voltage on VSyn Internal pull-down on H/HVSyn, VSyn H sync. pulse duration on H/HVSyn pin Proportion of H sync pulse to H period V sync. pulse duration Proportion of V sync pulse to V period Pin H/HVSyn Pins H/HVSyn, VSyn Pins H/HVSyn, VSyn 0.21 0.75 0.3 ms 0.5 Test Condit ions Min. 0 2.2 0 2.2 100 0.5 0.2 750 0.15 s 175 Value Typ. Max. 0.8 5 0.8 5 250 V V V V k s Units
Proportion of sync pulse length to H peri- Pin H/HVSyn, od for extraction as V sync pulse cap. on pin CO = 820pF Polarity detection time (after change) Pin H/HVSyn
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TDA9115
6.4 HORIZONTAL SECTION
Vcc = 12V, Tamb = 25C
Symbol PLL1 IRO C CO fHO fHO(0) fHOCapt f H O ( 0 ) ---------------------------f HO ( 0) T fHO/VHO VHO VHOThrfr Current load on RO pin Capacitance on CO pin Frequency of hor. oscillator Free-running frequency of hor. oscill. (1) Hor. PLL1 capture frequency (4) R RO=5.23k, CCO=820pF fHO(0) = 28.5kHz 27 29 28.5 390 150 29.9 122 1.5 mA pF kHz kHz kHz Parameter Test Condit ions Min. Value Typ. Max. Units
Temperature drift of free-running freq. (3)
-150
ppm/C
Average horizontal oscillator sensitivity
fHO(0) = 28.5kHz 1.4
19.6 6.0 5.0 2.60 3.30 3.85 2.8 3.4 4.0 1.6 6.4 3.05 3.55 4.15
kHz/V V V V V V V V 700 5 mA V V V 4.25 V % %
H. oscill. control voltage on pin HPLL1F VRefO=8V Threshold on H. oscill. control voltage on V =8V HPLL1F pin for tracking of EW with freq. RefO Control voltage on HPosF pin Bottom of hor. oscillator sawtooth(6) Top of hor. oscillator sawtooth(6) Input impedance on HFly input (2) Current into HFly input Voltage threshold on HFly input H flyback lock middle point (6) Low clamping voltage on HPLL2C pin(5) High clamping voltage on HPLL2C pin(5) Min. advance of H-drive OFF before middle of H flyback(7) Max. advance of H-drive OFF before middle of H flyback(8) Current into HOut output Duty cycle of H-drive signal Null asym. correction Null asym. correction No PLL2 phase modulation V(HFly) >VThrHFly At top of H flyback pulse
VHPosF VHOThrLo V HOThrHi PLL2 RIn(HFly) IInHFly VThrHFly V S(0) V BotHPLL2C V TopHPLL2C tph(min)/TH tph(max)/T H
HPOS (Sad01): 11111111b 10000000b 00000000b
300 0.6
500 0.7 4.0 1.6
3.75
4.0 0 44
H-drive outpu t on pin HOut IHOut tHoff/T H Output driven LOW Soft-start/Soft-stop value 48 85 30 mA % %
Picture geometry corrections through PLL1 & PLL2 tHph/T H H-flyback (center) static phase vs. sync signal (via PLL1), see Figure 7
HPOS (Sad01): 11111111b 00000000b
+11 -11
% %
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TDA9115
Symbol
Parameter
Test Condit ions Min.
Value Typ. Max.
Units
tPCAC/T H
PCAC (Sad11h) full span Contribution of pin cushion asymmetry VPOS at medium correction to phase of H-drive vs. static VSIZE at minimum phase (via PLL2), measured in corners (9 VSIZE at medium VSIZE at maximum PARAL (Sad12h) full span VPOS at medium VSIZE at minimum VSIZE at medium VSIZE at maximum VPOS at max. or min. VSIZE at minimum
1.0 1.8 2.8
% % %
tParalC/T H
Contribution of parallelogram correction to phase of H-drive vs. static phase (via PLL2), measured in corners (9)
1.75 2.2 2.8 1.75
% % % %
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must always be higher than the free-running frequency. The application must consider the spread of values of real electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate the free-running frequency is fHO(0)=0.12125/(R RO C CO) Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of about 500 and a resistance to ground of about 20k. Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit. Note 4: This capture range can be enlarged by external circuitry. Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state. Note 6: Internal threshold. See Figure 7. Note 7: The tph(min)/T H parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2 C high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 7. Note 8: The tph(max)/T H parameter is fixed by the application. For correct operation of asymmetry corrections through dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 7 . Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
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TDA9115
6.5 VERTICAL SECTION
VCC = 12V, Tamb = 25C
Symbol Parameter Test Conditions Min. AGC-controlled vertical oscillator sawtooth; VRefO = 8V R L(VAGCCap) VVOB VVOT tVODis fVO(0) fVOCapt V V Odev -------------------------------V ( 16 )
V Oamp
Value Typ. Max.
Units
Ext. load resistance on VAGCCap pin(10) Sawtooth bottom voltage on VCap pin(11) Sawtooth top voltage on VCap pin Sawtooth Discharge time Free-running frequency AGC loop capture frequency Sawtooth non-linearity (12)
Vamp/Vamp(R=) 1% No load on VOscF pin (11) AGC loop stabilized V sync present No V sync C VCap=150nF C VCap=150nF CVCap=150nF AGC loop stabilized, (12) AGC loop stabilized, (13) tVR=1/4 TVR(15) tVR=3/4 TVR AGC loop stabilized, (14) tVR=1/2 TVR(15) CCOR(Sad0A): x0000000b x1000000b x1111111b AGC loop stabilized fVOCapt(min)fVOfVOCapt(max)
65 1.8 1.9 5 4.9 80 100 50 0.5 185 2.0
M V V V s Hz Hz %
V V OS - cor ------------------------------V VOamp
S-correction range
-5 +5
% %
V VOC - cor -------------------------------V VOamp
C-correction range
-3 0 +3 200
% % %
ppm/Hz
V V Oamp ---------------------------------------V VOamp fV O
Frequency drift of sawtooth amplitude(17)(18)
Vertical outpu t drive signal (on pin VOut);VRefO = 8V Vmid(VOut) Middle point on VOut sawtooth
VPOS (Sad08): x0000000b x1000000b x1111111b VSIZE (Sad07): x0000000b x1000000b x1111111b
3.65
3.2 3.5 3.8 2.25 3.0 3.75 3.8
3.3
V V V V V V V
Vamp VoffVOut IVOut VVEHT V amp -------------- ----------- --------------V amp V V E H T
Amplitude of VOut sawtooth (peak-to-peak voltage)
2.5
3.5
Level on VOut pin at V-drive "off" I2Cbit VOutEn at 0 Current delivered by VOut output Control input voltage range on VEHTIn pin Breathing compensation V VEHT>VRefO V VEHT(min)VVEHTVRefO -5 1
5 VRefO 0 2.5
mA V %/V %/V
Note 10: Value of acceptable cumulated parasitic load resistance due to humidity, AGC storage capacitor leakage, etc., for less than 1% of Vamp change.
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Note 11: The threshold for VVOB is generated internally and routed to VOscF pin. Any DC current on this pin will influence the value of VVOB. Note 12: Maximum of deviation from an ideally linear sawtooth ramp at null SCOR (Sad09 at x0000000b) and null CCOR (Sad0A at x1000000b). The same rate applies to V-drive signal on VOut pin. Note 13: Maximum SCOR (Sad09 at x1111111b), null CCOR (Sad0A at x1000000b). Note 14: Null SCOR (Sad09 at x0000000b). Note 15: "tVR" is time from the beginning of vertical ramp of V-drive signal on VOut pin. "TVR" is duration of this ramp, see chapter TYPICAL OUTPUT WAVEFORMS and Figure 19. Note 16: VVOamp = VVOT -VVOB Note 17: The same rate applies to V-drive signal on VOut pin. Note 18: Informative, not tested on each unit.
6.6 EW DRIVE SECTION
VCC = 12V, Tamb = 25C
Symbol VEW IEWOut VHEHT Parameter Output voltage on EWOut pin Current sourced by EWOut output Control voltage range on HEHTIn pin
(19)(20)(21)(28) tVR=1/2 TVR(15)
Test Conditions Min. 1.8 -1.5 1
Value Typ. Max. 6.5 0 VRefO
Units V mA V
VEW-DC
DC component of the EW-drive signal on EWOut pin
HSIZE (Sad10h): 00000000b 10000000b 11111111b
(19)((20)
2 3.25 4.5
V V V
V E W - DC ---------------------------V HE H T V E W - DC ----------------------------------V E W - D C T
Breathing compensation on VEW-DC
tVR=1/2 TVR(15) VHEHT>VRefO VHEHT(min)VHEHTVRefO
0 -0.125 100
V/V V/V ppm/C
Temperature drift of DC compo- (18)(19)(21)(28) nent of the EW-drive signal on tVR=1/2TVR(15) EWOut pin
(19)(21)(22)(23)(24)(28)
VEW-PCC
Pin cushion correction component of the EW-drive signal on EWOut pin
VSIZE at maximum PCC (Sad0C): x0000000b x1000000b x1111111b Tracking with VSIZE : PCC at x1000000b VSIZE (Sad07): x0000000b x1000000b
(19)(22)(25)(27)(28)
0 0.7 1.5
V V V
0.25 0.5
V V
V E W - P C C [ tvr = 0 ] -------------------------------------------------------EW - P C C [ t vr = TV R ]
Tracking of PCC component of the EW-drive signal with vertical position adjustment
PCC at x1111111b VPOS (Sad08): x0000000b x1111111b
0.52 1.92
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Symbol
Parameter Keystone correction component of the EW-drive signal on EWOut pin
Test Conditions Min.
(20)(21)(22)(25)(26)(28)
Value Typ. Max.
Units
VEW-Key
KEYST (Sad0D): x0000000b x1111111b
0.4 -0.4 0 20
V V %/V %/V
V EW -------------------------------------------------------- V EW [ f ma x ] V HO
Tracking of EW-drive signal with VHO>VHOThrfr horizontal frequency (30) VHO(min)VHOV HOThrfr
(23)(24)
V E W - A C --------------------------------------------------V E W - A C V H E HT
Breathing compensation on VEW-AC(29)
VHEHT>VRefO VHEHT(min)VHEHTVRefO
0 1.75
%/V %/V
Note 19: KEYST at medium (neutral) value. Note 20: PCC at minimum value. Note 21: VPOS at medium (neutral) value. Note 22: HSIZE at minimum value. Note 23: Defined as difference of (voltage at tVR=0) minus (voltage at tVR=1/2 TVR). Note 24: Defined as difference of (voltage at tVR=TVR) minus (voltage at tVR=1/2 TVR). Note 25: VSIZE at maximum value. Note 26: Difference: (voltage at tVR=0) minus (voltage at tVR=TVR). Note 27: Ratio "A/B"of parabola component voltage at tVR=0 versus parabola component voltage at tVR=TVR. See Figure 2. Note 28: VHEHT>VRefO, VVEHT>VRefO Note 29: VEW-AC is the sum of all components other than VEW-DC (contribution of PCC and keystone correction). Note 30: More precisely tracking with voltage on HPLL1F pin which itself depends on frequency at a rate given by external components on PLL1 pins. VEW[fmax] is the value at condition VHO>VHOThrfr.
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6.7 DYNAMIC CORRECTION OUTPUTS SECTION
VCC = 12V, Tamb = 25C
Symbol Parameter Test Conditi ons Min. Vertical Dynamic Correction output VDyCor IVDyCor V VD-DC Current sunk from VDyCor output DC component of the drive signal on VDyCor output RL(VDyCor)=10k -1.5 4 -0.1 mA V Value Typ. Max. Units
IVVD-VI
Amplitude of V-parabola on VDyCor output (21)
VSIZE at medium VDC-AMP (Sad15h): xxxxxx00 xxxxxx01 xxxxxx10 xxxxxx11 VDC-AMP at maximum VSIZE (Sad07): x0000000b x1111111b
0.25 0.50 0.75 1.00
V V V V
0.6 1.6
V V
V VD - V [ tvr = 0 ] -------------- ----------- ---------------------- V V D - V [ t vr = TV R ]
VDC-AMP at maximum Tracking of V-parabola on VDyCor VPOS (Sad08): output with vertical position (31) x0000000b x1111111b
0.52 1.92
Note 31: Ratio "A/B"of vertical parabola component voltage at tVR=0 versus vertical parabola component voltage at tVR=TVR.
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6.8 DC/DC CONTROLLER SECTION
VCC = 12V, Tamb = 25C
Symbol R B+FB AOLG fUGBW IRI IBComp ABISense VThrBIsCurr IBISense IBOut VBOSat VBReg tBTrigDel / TH Parameter Test Condit ions Min. 5 100 6 -0.2 -0.5 0.5 3 1.98 2.1 -1 0 0.25 4.7 4.8 16 10 0.35 5.0 2.22 V A mA V V % 2.0 Value Typ. Max. k dB MHz A mA mA Units
Ext. resistance applied between BComp output and BRegIn input Open loop gain of error amplifier Low frequency(18) on BRegIn input Unity gain bandwidth of error am- (18) plifier on BRegIn input Bias current delivered by regulation input BRegIn
Output current capability of BComp output. Voltage gain on BISense input Threshold voltage on BISense input corresponding to current limitation Input current sourced by BISense input Output current capability of BOut output Saturation voltage of the internal output IBOut=10mA transistor on BOut Regulation reference for BRegIn voltage(33) Delay of BOut "Off-to-On" edge after middle of flyback pulse, as part of TH VRefO=8V BOutPh = "0" HBOutEn = "Enable" HBOutEn = "Disable" (32)
(34)
Note 32: A current sink is provided by the BComp output while BOut is disabled: Note 33: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is stabilized. Note 34: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut "Off-to-On" edge with horizontal flyback signal. Refer to chapter "DC/DC controller" for more details.
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6.9 MISCELLANEOUS
VCC = 12V, Tamb = 25C
Symbol Parameter Test Condit ions Min. Vertical blanking and horizon tal lock indication composite outpu t HLckVBk ISinkLckBk Sink current to HLckVBk pin
(35)
Value Typ. 100 Max.
Units
A
V.blank No VOLckBk Output voltage on HLckVBk output Yes No Yes Horizontal moire canceller VAC-HMoire VDC-HMoire Rext=10k HMOIRE (Sad02): H-moire pulse amplitude on HMoire pin x0000000b x1111111b DC level on HMoire pin Rext=10k
H.lock Yes Yes No No 0.1 1.1 5 6 V V V V
0.1 2.1 0.1
V V V
Vertical moire canceller VV-moire
VMOIRE (Sad0Bh): Amplitude of modulation of V-drive sigx0000000b nal on VOut pin by vertical moire. x1111111b
Input threshold on XRay input(36) Delay time between XRay detection event and protection action VCC value for start of operation at VCC ramp-up(37) VCC value for stop of operation at VCC ramp-down (37) Threshold for start/stop of H-drive signal Threshold for start/stop of B-drive signal Threshold for full operational duty cycle of H-drive and B-drive signals Normal operation Voltage on HPosF pin as function of ad- HPOS (Sad01) justment of HPOS register 00000000b 11111111b 7.65
0 3 7.9 2TH 8.5 6.5 8.2
mV mV V
Protection function s VThrXRay tXRayDelay VCCEn VCCDis
V V
Control voltages on HPosF pin for Soft start/stop operation(18) VHOn VBOn VHBNorm f 1 1.7 2.4 V V
VHPos
3.85 2.60
4.0 2.8
4.15 3.05
V V
Note 35: Current sunk by the pin if the external voltage is higher than one the circuit tries to force. Note 36: The threshold is equal to actual VRefO. Note 37: In the regions of V CC where the device's operation is disabled, the H-drive, V-drive and B+-drive signals on HOut, VOut and BOut pins, resp., are inhibited, the I2C Bus does not accept any data.
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7 - TYPICAL OUTPUT WAVEFORMS
Note (38)
Function Sad Pin Byte x0000000 Vertical Size 07 VOut x1111111 V amp(max)
Vmid(VOut)
Waveform V amp(min)
Effect on Screen
Vmid(VOut)
x0000000
3.5V
Vmid(VOut)
Vertical Position
08
VOut
x1000000
Vmid(VOut)
3.5V
x1111111
Vmid(VOut)
3.5V
x0000000: Null S-correction 09 VOut x1111111: Max.
VVOamp
VVOS-cor VVOamp
0
1/4 VR T
3/4 VR TVR t T VR
VVOamp
x0000000
0
VVOC-cor
1/2 VR T
TVR t VR
C-correction
0A
VOut
x1000000 : Null
VVOamp
VVOamp
x1111111
0
VVOC-cor
1/2 VR T
TVR t VR
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Function
Sad
Pin
Byte x0000000: Null Vamp
(n-1)TV
Waveform
Effect on Screen
Vertical moire amplitude
nTV
(n+1)TV
t
0B
VOut x1111111: Vamp Max.
(n-1)TV nTV
VV-moire
(n+1)TV
t
00000000 Horizontal size 10h EWOut 11111111
VEW-DC(min)
0
1/2 VR T
TVR t VR
VEW-DC(max)
0
1/2 VR T VEW-DC
TVR t VR
x0000000 Keystone correction 0D EWOut x1111111
VEW-key
VEW-key
VEW-DC
VEW-PCC(min)
x0000000 Pin cushion correction
0
1/2 VR T
T VR t VR
0C
EWOut x1111111
VEW-PCC(max)
0 tParalC(min)
1/2 VR T
static phase
T VR tVR
x0000000 Internal Parallelogram correction
0
1/2 VR T
12h
T VR t VR
tParalC(max)
x1111111
0
static phase
1/2 VR T
T VR t VR
static H-phase
tPCAC(max)
x0000000 Internal Pin cushion asymmetry correction
0
1/2 VR T
T VR t VR
11h
tPCAC(max)
x1111111
0
static H-phase
1/2 VR T
T VR t VR
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Function
Sad
Pin
Byte
Waveform
VVD-V(max)
Effect on Screen VDyCorPo
VVD-DC
Vertical dynamic correction amplitude
xxxxxx11 15h VDyCor xxxxxx00
0 0
1/2 VR T
T VR t VR
Application dependent
VVD-V(max)
VVD-DC
T VR t VR
1/2 VR T
Note 38: For any H and V correction component of the waveforms on EWOut and VOut pins and for internal waveform for corrections of H asymmetry, displayed in the table, weight of the other relevant components is nullified (minimum for parabola, S-correction, medium for keystone, all corner corrections, C-correction, parallelogram, parabola asymmetry correction, written in corresponding registers).
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8 - I2C BUS CONTROL REGISTER MAP
The device slave address is 8C in write mode and 8D in read mode. Bold weight denotes default value at Power-On-Reset. I2C Bus data in the adjustment register is buffered and internally applied with discharge of the vertical oscillator . In order to ensure compatibility with future devices, all "Reserved" bits should be set to 0.
Sad 00 01 1 HMoire 1: Separated 0: Combined 0 0 0 D7 D6 D5 D4 Reserved D3 D2 D1 D0 WRITE MODE (SLAVE ADDRESS = 8C)
HPOS HMOIRE
0 0 0
(Horizontal position)
0 0 0
Reserved
(Horizontal moire amplitude)
0 0 0 0
02 03 04 05 06
Reserved Reserved Reserved BOutPol 0: Type N BOutPh 0: H-flyback 1: H-drive EWTrHFr 0: No tracking Reserved Reserved Reserved Reserved Reserved Reserved
VSIZE
1 0 0
(Vertical size)
0 0 0 0
07
08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15
VPOS
1 1 1 0 1 1 0 0 0 0 0 0 0
(Vertical position)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
SCOR
0
(S-correction)
0
CCOR
0
(C-correction)
0 0
VMOIRE
0
(Vertical moire amplitude) (Pin cushion correction)
0 0
PCC
0
KEYST
0
(Keystone correction)
Reserved Reserved
HSIZE
1 Reserved Reserved 0 1 1 0 0 0 0
(Horizontal size)
0 0 0 0 0 0 0 0 0
Reserved
PCAC
0
(Pin cushion asymmetry correction)
0 0
PARAL
0
(Parallelogram correction)
Reserved Reserved Reserved
VDC-AMP
0 0
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Sad 16
D7 XRayReset 0: No effect 1: Reset TV 0: Off(39)
D6 VSyncAuto 1: On TH 0: Off(39)
D5 VSyncSel 0:Comp 1:Sep TVM 0: Off(39)
D4 0 THM 0: Off(39)
D3 0 BOHEdge 0: Falling
D2 PLL1Pump 1: Fast 0: Slow HBOutEn 0: Disable
D1 PLL1InhEn 1: On VOutEn 0: Disable
D0 HLockEn 1: On BlankMode 1: Perm.
17
Note 39: The TV, TH, TVM and THM bits are for testing purposes and must be kept at 0 by application.
Description of I2C Bus switches Write-to bits Sad02/D7 - HMoire Horizontal Moire characteristics 0: Adapted to an architecture with EHT generated in deflection section 1: Adapted to an architecture with separated deflection and EHT sections Sad06/D7 - BOutPol Polarity of B+ drive signal on BOut pin 0: adapted to N type of power MOS - high level to make it conductive 1: adapted to P type of power MOS - low level to make it conductive Sad07/D7 - BOutPh Phase of start of B+ drive signal on BOut pin 0: Just after horizontal flyback pulse 1: With one of edges of line drive signal on HOut pin, selected by BOHEdge bit Sad08/D7 - EWTrHFr Tracking of all corrections contained in waveform on pin EWOut with Horizontal Frequency 0: Not active 1: Active Sad16/D0 - HLockEn Enable of output of Horizontal PLL1 Lock/unlock status signal on pin HLckVBk 0: Disabled, vertical blanking only on the pin HLckVBk 1: Enabled Sad16/D1 - PLL1InhEn Enable of Inhibition of horizontal PLL1 during extracted vertical synchronization pulse 0: Disabled, PLL1 is never inhibited 1: Enabled Sad16/D2 - PLL1Pump Horizontal PLL1 charge Pump current 0: Slow PLL1, low current 1: Fast PLL1, high current Sad16/D5 - VSyncSel Vertical Synchronization input Selection between the one extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn. No effect if VSyncAuto bit is at 1. 0: V. sync extracted from composite signal on H/HVSyn pin selected 1: V. sync applied on VSyn pin selected Sad16/D6 - VSyncAuto Vertical Synchronization input selection Automatic mode. If enabled, the device automatically selects between the vertical sync extracted from composite HV signal on pin H/HVSyn and the one on pin VSyn, based on detection mechanism. If both are present, the one coming first is kept. 0: Disabled, selection done according to bit
VSyncSel
1: Enabled, the bit VSyncSel has no effect Sad16/D7 - XRayReset Reset to 0 of XRay effected with ACK bit of I2C Bus data transfer into register containing the XRayReset bit. 0: No effect 1: Reset with automatic return of the bit to 0 This bit is not latched, it will return to 0 by itself. Sad17/D0 - BlankMode Blanking operation Mode 0: Blanking pulse starting with detection of vertical synchronization pulse and ending with end of vertical oscillator discharge
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(start of vertical sawtooth ramp on the VOut pin) 1: Permanent blanking - high blanking level in composite signal on pin HLckVBk is permanent Sad17/D1 - VOutEn Vertical Output Enable 0: Disabled, VoffVOut on VOut pin (see 6.5 Vertical section) 1: Enabled, vertical ramp with vertical position offset on VOut pin
Sad17/D2 - HBOutEn Horizontal and B+ Output Enable 0: Disabled, levels corresponding to "power transistor off" on HOut and BOut pins (high for HOut, high or low for BOut, depending on BOutPol bit). 1: Enabled, horizontal deflection drive signal on HOut pin providing that it is not inhibited by another internal event (activated XRay protection). B+ drive signal on BOut pin. Programming the bit to 1 after prior value of 0, will initiate soft start mechanism of horizontal drive and of B+ DC/DC convertor Sad17/D3 - BOHEdge Selection of Edge of Horizontal drive signal to phase B+ drive Output signal on BOut pin. Only applies if the bit BOutPh is set to 1, otherwise BOHEdge has no effect. 0: Falling edge 1: Rising edge Sad17/D4,D5,D6,D7 - THM, TVM, TH, TV Test bits. They must be kept at 0 level by application S/W.
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9 - OPERATING DESCRIPTION
9.1 SUPPLY AND CONTROL
9.1.1 Power supply and voltage references The device is designed for a typical value of power supply voltage of 12 V. In order to avoid erratic operation of the circuit at power supply ramp-up or ramp-down, the value of VCC is monitored. See Figure 1 and electrical specifications. At switch-on, the device enters a "normal operation" as the supply voltage exceeds VCCEn and stays there until it decreases below VCCDis. The two thresholds provide, by their difference, a hysteresis to bridge potential noise. Outside the "normal operation", the signals on HOut, BOut and VOut outputs are inhibited and the I2C bus interface is inactive (high impedance on SDA, SCL pins, no ACK), all I2C bus control registers being reset to their default values (see chapter I 2C BUS CONTROL REGISTER MAP on page 20). Figure 1. Supply voltage monitoring
V(Vcc) V CC VCCEn
hysteresis
description, refer to corresponding Philips I2C bus specification. This device is an I2C bus slave, compatible with fast (400kHz) I2C bus protocol, with write mode slave address of 8C. Integrators are employed at the SCL (Serial Clock) input and at the input buffer of the SDA (Serial Data) input/output to filter off the spikes of up to 50ns. The device supports multiple data byte messages (with automatic incrementation of the I2C bus subaddress) as well as repeated Start Condition for I2C bus subaddress change inside the I2C bus messages. All I2C bus registers with specified I2C bus subaddress are of WRITE ONLY type. For the I2C bus control register map, refer to chapter I2C BUS CONTROL REGISTER MAP on page 20.
9.2 SYNC. PROCESSOR
9.2.1 Synchronization signals The device has two inputs for TTL-level synchronization signals, both with hysteresis to avoid erratic detection and with a pull-down resistor. On H/ HVSyn input, pure horizontal or composite horizontal/vertical signal is accepted. On VSyn input, only pure vertical sync. signal is accepted. Both positive and negative polarities may be applied on either input, see Figure 2. Polarity detector and programmable inverter are provided on each of the two inputs. The signal applied on H/HVSyn pin, after polarity treatment, is directly lead to horizontal part and to an extractor of vertical sync. pulses, working on principle of integration, see Figure 3. The vertical sync. signal applied to the vertical deflection processor is selected between the signal extracted from the composite signal on H/HVSyn input and the one applied on VSyn input. The selector is controlled by VSyncSel I2C bus bit. Besides the polarity detection, the device is capable of detecting the presence of sync. signals on each of the inputs and at the output of vertical sync. extractor. The device is equipped with an automatic mode (switched on or off by VSyncAuto I2C bus bit) that uses the detection information.
V CCDis
Disabled
Normal operation
Disabled
t
Internal thresholds in all parts of the circuit are derived from a common internal reference supply VRefO that is lead out to RefOut pin for external filtering against ground as well as for external use with load currents limited to IRefO. The filtering is necessary to minimize interference in output signals, causing adverse effects like e.g. jitter. 9.1.2 I2C Bus Control The I2C bus is a 2 line bi-directional serial communication bus introduced by Philips. For its general
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Figure 2. Horizontal sync signal
Positive TH tPulseHSyn
Negative
Figure 3. Extraction of V-sync signal from H/V-sync signal
H/V-sync TH Internal Integration textrV Extracted V-sync tPulseHsyn
9.2.2 Automatic sync. selection mode I2C bus bit VSyncAuto is set to 1. In this mode, the device itself controls the I2C bus bits switching the polarity inverters and the vertical sync. signal selector (VSyncSel), using the information provided by detection circuitry. If both extracted and pure vertical sync. signals are present, the one already selected is maintained. No intervention of the MCU is necessary.
9.3 HORIZONTAL SECTION
9.3.1 General The horizontal section consists of two PLLs with various adjustments and corrections, working on horizontal deflection frequency, then phase shifting and output driving circuitry providing H-drive signal on HOut pin. Input signal to the horizontal section is output of the polarity inverter on H/ HVSyn input. The device ensures automatically that this polarity be always positive. 9.3.2 PLL1 The PLL1 block diagram is in Figure 5. It consists of a voltage controlled oscillator (VCO), a shaper with adjustable threshold, a charge pump with inhibition circuit, a frequency and phase comparator and timing circuitry. The goal of the PLL1 is to make the VCO ramp signal match in frequency the sync. signal and to lock this ramp in phase to the sync. signal, with a possibility to adjust a perma-
nent phase offset. On the screen, this offset results in the change of horizontal position of the picture. The loop, by tuning the VCO accordingly, gets and maintains in coincidence the rising edge of input sync. signal with signal REF1, which is derived from the VCO ramp by a comparator with threshold adjustable through HPOS I2C bus control. The coincidence is identified and flagged by lock detection circuit on pin HLckVBk . The charge pump provides positive and negative currents charging the external loop filter on HPosF pin. The loop is independent of the trailing edge of sync. signal and only locks to its leading edge. By design, the PLL1 does not suffer from any dead band even while locked. The speed of the PLL1 depends on the current value provided by the charge pump. While not locked, the current is very low, to slow down the changes of VCO frequency and thus protect the external power components at sync. signal change. In locked state, the currents are much higher, two different values being selectable via PLL1Pump I2C bus bit to provide a mean to control the PLL1 speed by S/W. Lower values make the PLL1 slower, but more stable. Higher values make it faster and less stable. In general, the PLL1 speed should be higher for high deflection frequencies. The response speed and stability (jitter level) depends on the choice of external components making up the loop filter. A "CRC" filter is generally used (see Figure 4 on page 25).
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Figure 4. H-PLL1 filter configuration
HPLL1F
9
pump output to high impedance state. The inhibition mechanism can be disabled through PLL1Pump I2C bus bit. The Figure 7, in its upper part, shows the position of the VCO ramp signal in relation to input sync. pulse for three different positions of adjustment of horizontal position control HPOS.
R2 C2
C1
The PLL1 is internally inhibited during extracted vertical sync. pulse (if any) to avoid taking into account missing or wrong pulses on the phase comparator. Inhibition is obtained by forcing the charge Figure 5. Horizontal PLL1 block diagram
PLL1InhEn V-sync (extracted) (I2C) PLL1 Sync Polarity H/HVSyn 1 INPUT INTERFACE COMP Low Extracted V-sync REF1 PLL1Pump (I2C) Lock Status (pin & I2C) HPLL1F R0 C0 HOscF 9 LOCK DETECTOR PLL INHIBITION CHARGE PUMP HPosF 10 VCO HOSC 8 6 4
High
SHAPER
HPOS (I2C)
Figure 6. Horizontal oscillator (VCO) schematic diagram
4 I0 (PLL1 filter) HPLL1F 9 VHO + 4 I0 RO 8 from charge pump 6 CO
VHOThrHi VHOThrLo
HOscF + +
V HOThrHi
I0
2
RS Flip-Flop
VHOThrLo
VCO discharge control
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9.3.3 Voltage controlled oscillator The VCO makes part of both PLL1 and PLL2 loops, being an "output" to PLL1 and "input" to PLL2. It delivers a linear sawtooth. Figure 6 explains its principle of operation. The linears are obtained by charging and discharging an external capacitor on pin CO, with currents proportional to the current forced through an external resistor on pin RO, which itself depends on the input tuning voltage VHO (filtered charge pump output). The rising and falling linears are limited by VHOThrLo and VHOThrHi thresholds filtered through HOscF pin. At no signal condition, the VHO tuning voltage is clamped to its minimum (see chapter ELECTRICAL PARAMETERS AND OPERATING CONDITIONS, part horizontal section), which corresponds to the free-running VCO frequency fHO(0). Refer to Note1 for the formula to calculate this frequency using external components values. The ratio between the frequency corresponding to maximum VHO and the one corresponding to minimum VHO (free-running frequency) is about 4.5. This range can easily be increased in the application. The PLL1 can only lock to input frequencies falling inside these two limits. 9.3.4 PLL2 The goal of the PLL2 is, by means of phasing the signal driving the power deflection transistor, to lock the middle of the horizontal flyback to a certain threshold of the VCO sawtooth. This internal threshold is affected by geometry phase corrections, like e.g., parallelogram. The PLL2 is much faster than PLL1 to be able to follow the dynamism of this phase modulation. The PLL2 control current (see Figure 7) is significantly increased during discharge of vertical oscillator (during vertical retrace period) to be able to make up for the difference of dynamic phase at the bottom and at the top of the picture. The PLL2 control current is integrated on the external filter on pin HPLL2C to obtain smoothed voltage, used, in comparison with VCO ramp, as a threshold for H-drive rising edge generation.
As both leading and trailing edges of the H-drive signal in the Figure 7 must fall inside the rising part of the VCO ramp, an optimum middle position of the threshold has been found to provide enough margin for horizontal output transistor storage time as well as for the trailing edge of H-drive signal with maximum duty cycle. Yet, the constraints thereof must be taken into account while considering the application frequency range and H-flyback duration. The Figure 7 also shows regions for rising and falling edges of the H-drive signal on HOut pin. As it is forced high during the H-flyback pulse and low during the VCO discharge period, no edge during these two events takes effect. The flyback input configuration is in Figure 8. 9.3.5 Dynamic PLL2 phase control The dynamic phase control of PLL2 is used to compensate for picture asymmetry versus vertical axis across the middle of the picture. It is done by modulating the phase of the horizontal deflection with respect to the incoming video (synchronization). Inside the device, the threshold VS(0) is compared with the VCO ramp, the PLL2 locking the middle of H-flyback to the moment of their match. The dynamic phase is obtained by modulation of the threshold by correction waveforms. Refer to Figure 12 and to chapter TYPICAL OUTPUT WAVEFORMS. The correction waveforms have no effect in vertical middle of the screen (for middle vertical position). As they are summed, their effect on the phase tends to reach maximum span at top and bottom of the picture. As all the components of the resulting correction waveform (linear for parallelogram correction and parabola of 2nd order for Pin cushion asymmetry correction) are generated from the output vertical deflection drive waveform, they both track with real vertical amplitude and position (including breathing compensation), thus being fixed on the screen. Refer to I2C BUS CONTROL REGISTER MAP on page 20 for details on I2C bus controls.
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Figure 7. Horizontal timing diagram
t Hph
min max
H-sync (polarized) PLL1 lock REF1 (internal) VHPosF H-Osc (VCO)
max. med. min.
HPOS (I2C)
max. med. min.
The PLL2 is followed by a rapid phase shifting which accepts the signal from H-moire canceller (see sub chapter Horizontal moire cancellation on page 27) The output stage consists of a NPN bipolar transistor, the collector of which is routed to HOut pin (see Figure 9).
PLL1
Figure 9. HOut configuration
26 HOut int. ext.
VHOThrHi VS(0)
VHOThrLo 7/8T H TH VThrHFly tS
PLL2 control current H-drive (on HOut) H-drive region H-drive region
+ -
ON
tHoff
OFF
ON
forced low
forced high tph(max)
inhibited tS: HOT storage time
Figure 8. HFly input configuration
~500 HFly 12 ~20k
ext.
int. GND
9.3.6 Output section The H-drive signal is inhibited (high level) during flyback pulse, and also when VCC is too low, when I2C bus bit HBOutEn is set to 0 (default position).
PLL2
H-flyback
Non-conductive state of HOT (Horizontal Output Transistor) must correspond to non-conductive state of the device output transistor. 9.3.7 Soft-start and soft-stop on H-drive The soft-start and soft-stop procedure is carried out at each switch-on or switch-off of the H-drive signal via HBOutEn I2C bus bit to protect external power components. By its second function, the external capacitor on pin HPosF is used to time out this procedure, during which the duty cycle of Hdrive signal starts at its maximum ("tHoff/TH for soft start/stop" in electrical specifications) and slowly decreases. This is controlled by voltage on pin HPosF. See Figure 10 and sub chapter Safety functions on page 33. 9.3.8 Horizontal moire cancellation The horizontal moire canceller is intended to blur a potential beat between the horizontal video pixel period and the CRT pixel width, which causes visible moire patterns in the picture. On pin HMoire, it generates a square line-synchronized waveform with amplitude adjustable through HMOIRE I2C bus control. The behaviour of horizontal moire is to be optimised for different deflection design configurations using HMoire I2C bus bit. This bit is to be kept at 0 for common architecture (B+ and EHT common regulation) and at 1 for separated architecture (B+ and EHT each regulated separately).
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Figure 10. Control of HOut and BOut at start/stop at nominal Vcc
V(HPosF) VHPosMax VHBNorm V BOn V HOn Soft start Start HOut Start BOut Normal operation Soft stop Stop BOut Stop HOut t HOut H-duty cycle BOut (positive) B-duty cycle 0% 100% VHPosMin minimum value
HPOS (I2C) range
maximum value
9.4 VERTICAL SECTION
9.4.1 General The goal of the vertical section is to drive vertical deflection output stage. It delivers a sawtooth waveform with an amplitude independent of deflection frequency, on which vertical geometry corrections of C- and S-type are superimposed (see chapter TYPICAL OUTPUT WAVEFORMS). Block diagram is in Figure 11. The sawtooth is obtained by charging an external capacitor on pin VCap with controlled current and by discharging it via transistor Q1. This is controlled by the CONTROLLER. The charging starts when the voltage across the capacitor drops below VVOB threshold. The discharging starts either when it exceeds VVOT threshold or a short time after arrival of synchronization pulse. This time is necessary for the AGC loop to sample the voltage at the top of the sawtooth. The V VOB reference is routed out onto VOscF pin in order to allow for further filtration. The charging current influences amplitude and shape of the sawtooth. Just before the discharge, the voltage across the capacitor on pin VCap is sampled and stored on a storage capacitor connected on pin VAGCCap. During the following vertical period, this voltage is compared to internal reference REF (VVOT), the result thereof controlling the gain of the transconductance amplifier providing the charging current. Speed of this AGC loop depends on the storage capacitance on pin
VAGCCap. On the screen, this corresponds to stabilized vertical size of picture. After a change of frequency on the sync. input, the stabilization time depends on the frequency difference and on the capacitor value. The lower its value, the shorter the stabilization time, but on the other hand, the lower the loop stability. A practical compromise is a capacitance of 470nF. The leakage current of this capacitor results in difference in amplitude between low and high frequencies. The higher its parallel resistance RL(VAGCCap), the lower this difference. When the synchronization pulse is not present, the charging current is fixed. As a consequence, the free-running frequency fVO(0) only depends on the value of the capacitor on pin VCap. It can be roughly calculated using the following formula fVO(0) = 150nF C(VCap) . 100Hz
The frequency range in which the AGC loop can regulate the amplitude also depends on this capacitor. The C- and S-corrections of shape serve to compensate for the vertical deflection system non-linearity. They are controlled via CCOR and SCOR I2C bus controls. Shape-corrected sawtooth with regulated amplitude is lead to amplitude control stage. The dis-
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charge exponential is replaced by VVOB level, which, under control of the CONTROLLER, creates a rapid falling edge and a flat part before beginning of new ramp. Mean value of the waveform output on pin VOut is adjusted by means of VPOS I2C bus control, its amplitude through VSIZE I2C bus control. Vertical moire is superimposed. The biasing voltage for external DC-coupled vertical power amplifier is to be derived from VRefO voltage provided on pin RefOut, using a resistor divider, this to ensure the same temperature drift of mean (DC) levels on both differential inputs and to Figure 11. Vertical section block diagram
compensate for spread of VRefO value (and so mean output value) between particular devices. 9.4.2 Vertical moire To blur the interaction of deflection lines with CRT mask grid pitch that can generate moire pattern, the picture position is to be alternated at frame frequency. For this purpose, a square waveform at half-frame frequency is superimposed on the output waveform's DC value. Its amplitude is adjustable through VMOIRE I2C bus control,.
Charge current
Transconductance amplifier
OSC Cap.
VCap 22
Sampling
REF 20 VAGCCap Sampling Capacitance S-correction
Discharge VSyn 2 Synchro Polarity Controller Q1
SCOR (I2C) CCOR (I2C)
C-correction sawtooth discharge 18 VEHTIn
23 VOut
VVOB 19 VOscF
VMOIRE (I2C) VPOS (I2C)
VSIZE
(I2C)
9.5 EW DRIVE SECTION
The goal of the EW drive section is to provide, on pin EWOut, a waveform which, used by an external DC-coupled power stage, serves to compensate for those geometry errors of the picture that are symmetric versus vertical axis across the middle of the picture. The waveform consists of an adjustable DC value, corresponding to horizontal size, a parabola of 2nd order for "pin cushion" correction and a linear for "keystone" correction. All of them are adjustable via I2C bus, see I2C BUS CONTROL REGISTER MAP on page 20.
Refer to Figure 12, Figure 13 and to chapter TYPICAL OUTPUT WAVEFORMS. The correction waveforms have no effect in the vertical middle of the screen (if the VPOS control is adjusted to its medium value). As they are summed, the resulting waveform tends to reach its maximum span at top and bottom of the picture. The voltage at the EWOut is top and bottom limited (see parameter VEW). According to Figure 13, especially the bottom limitation seems to be critical for maximum horizontal size (minimum DC). Actually it is not critical since the parabola component must always be applied. As all the components of the resulting correction waveform are generated from the out-
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put vertical deflection drive waveform, they all track with real vertical amplitude and position (including breathing compensation), thus being fixed vertically on the screen. They are also affected by C- and S-corrections. The sum of components other than DC is affected by value in HSIZE I2C bus control in reversed sense. Refer to electrical specifications for value. The DC value, adjusted via HSIZE control, is also affected by voltage on HEHTIn input, thus providing a horizontal breathing compensation (see electrical specifications for value). The resulting waveform is conditionally multiplied with voltage on HPLL1F, which depends on
frequency. Refer to electrical specifications for value and more precision. This tracking with frequency provides a rough compensation of variation of picture geometry with frequency and allows to fix the adjustment ranges of I2C bus controls throughout the operating range of horizontal frequencies. It can be switched off by EWTrHFr I2C bus bit (off by default). The EW waveform signal is buffered by an NPN emitter follower, the emitter of which is directly routed to EWOut output, with no internal resistor to ground. It is to be biased externally.
Figure 12. Geometric corrections' schematic diagram
Controls: one-quadrant two-quadrant
VDC-AMP (I2C)
Vmid(VOut) 2 VOut 23 32 VDyCor
PCC (I2C)
Vertical ramp Tracking HEHTIn/HSize HSize
17
KEYST (I2C)
Tracking with Hor Frequency
HEHTIn
PCAC (I2C)
To horizontal dyn. phase control
24 EWOut
PARAL (I2C)
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Figure 13. EWOut output waveforms
V(EWOut) VEW-DC
VEW(max)
HSIZE (I2C)
VEW operating range
VRefO
VEW-Key
VEW-PCC
m imu min
non-authorized region
me
diu
m
um xim ma
VEW(min)
Keystone alone
PCC alone
Breathing compensation
VHEHT(min)
V(VCap) Vertical sawtooth
0 T VR 0 TVR
V(HEHT)
tVR
9.6 DYNAMIC CORRECTION OUTPUT SECTION
9.6.1 Vertical Dynamic Correction output VDyCor A parabola at vertical deflection frequency is available on pin VDyCor. Its amplitude is adjustable via VDC-AMP I2C bus control. It tracks with real vertical amplitude and position (including breathing compensation). It is also affected by C- and S-corrections. The use of this correction waveform is up to the application (e.g. dynamic focus).
9.7 DC/DC CONTROLLER SECTION
The section is designed to control a switch-mode DC/DC converter. A switch-mode DC/DC convertor generates a DC voltage from a DC voltage of different value (higher or lower) with little power losses. The DC/DC controller is synchronized to
horizontal deflection frequency to minimize potential interference into the picture. Its operation is similar to that of standard UC3842. The schematic diagram of the DC/DC controller is in Figure 14. The BOut output controls an external switching circuit (a MOS transistor) delivering pulses synchronized on horizontal deflection frequency, the phase of which depends on I2C bus configuration, see the table at the end of this chapter. Their duration depends on feedback provided to the circuit, generally a copy of DC/DC converter output voltage and a copy of current passing through the DC/DC converter circuitry (e.g. current through external power component). The polarity of the output can be controlled by BOutPol I2C bus bit. A NPN transistor open-collector is routed out to the BOut pin. During the operation, a sawtooth is to be found on pin BISense, generated externally by the application. According to BOutPh I2C bus bit, the R-S flipflop is set either at H-drive signal edge (rising or falling, depending on BOHEdge I2C bus bit), or a
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certain delay (tBTrigDel / TH) after middle of H-flyback. The output is set On at the end of a short pulse generated by the monostable trigger. Timing of reset of the R-S flip-flop affects duty cycle of the output square signal and so the energy transferred from DC/DC converter input to its output. A reset edge is provided by comparator C2 if the voltage on pin BISense exceeds the internal threshold VThrBIsCurr. This represents current limitation if a voltage proportional to the current through the power component or deflection stage is available on pin BISense. This threshold is affected by the voltage on pin HPosF, which rises at soft start and descends at soft stop. This ensures self-contained soft control of duty cycle of the output signal on pin BOut. Refer to Figure 10. Another condition for the reset of the R-S flip-flop, OR-ed with the one described before, is that the voltage on pin BISense exceeds the voltage VC1, which depends on the voltage applied on input BISense of the error amplifier O1. The two voltages are
BOHEdge BOutPh (I2C) (I2C) H-drive edge
Monostable
compared, and the reset signal generated by the comparator C1. The error amplifier amplifies (with a factor defined by external components) the difference between the input voltage proportional to DC/DC convertor output voltage and internal reference VBReg. Both step-up (DC/DC converter output voltage higher than its input voltage) and step-down (output voltage lower than input) are possible. DC/DC controller Off-to-On edge timing
BOutPh BOHEdge (Sad07/ D7) 0 1 1 (Sad17/ D3) 0 1 Timing of Off-to-O n transition on BOut outpu t
don't care Middle of H-flyback plus tBTrigDel Falling edge of H-drive signal Rising edge of H-drive signal
Figure 14. DC/DC converter controller block diagram
H-flyback (+delay) VBReg Feedback BRegIn + O1 2R
~500ns I1 I2 N type
R
VCC
VC1
+ -
C1
S R
BOut Q P type BOutPol (I2C) HBOutEn XRayAlarm (I2C) I3
BComp VThrBIsCurr Soft start HPosF BIsense
+
C2
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9.8 MISCELLANEOUS
9.8.1 Safety functions The safety functions comprise supply voltage monitoring with appropriate actions, soft start and soft stop features on H-drive and B-drive signals on HOut and BOut outputs and X-ray protection. For supply voltage supervision, refer to paragraph Power supply and voltage references on page 23 and Figure 1. A schematic diagram putting together all safety functions and composite PLL1 lock and V-blanking indication is in Figure 15. 9.8.2 Soft start and soft stop functions For soft start and soft stop features for H-drive and B-drive signal, refer to paragraph Soft-start and soft-stop on H-drive on page 27 and sub chapterDC/DC CONTROLLER SECTION on page 31, respectively. See also the Figure 10. Regardless why the H-drive or B-drive signal are switched on or off (I2C bus command, power up or down, X-ray protection), the signals always phase-in and
phase-out in the way drawn in the figure, the first to phase-in and last to phase-out being the H-drive signal, which is to better protect the power stages at abrupt changes like switch-on and off. The timing of phase-in and phase-out only depends on the capacitance connected to HPosF pin which is virtually unlimited for this function. Yet it has a dual function (see paragraph PLL1 on page 24), so a compromise thereof is to be found. 9.8.3 X-ray protection The X-ray protection is activated if the voltage level on XRay input exceeds VThrXRay threshold. As a consequence, the H-drive and B-drive signals on HOut and BOut outputs are inhibited (switched off) after a 2-horizontal deflection line delay provided to avoid erratic excessive X-ray condition detection at short parasitic spikes. This protection is latched; it may be reset either by VCC drop or by I2C bus bit XRayReset (see chapter I2C BUS CONTROL REGISTER MAP on page 20).
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Figure 15. Safety functions - block diagram
HBOutEn I2C V CCEn V CCDis 29 Vcc VCC supervision + _ SOFT START & STOP HPosF (timing) 10
XRayReset I 2C XRay 25 VThrXRay HFly 12 VThrHFly VOutEn I 2C H-VCO discharge control + _ R In Out
R S
Q
:2
B-drive inhibit H-drive inhibit H-drive inhibition (overrule)
+ _
V-drive inhibition
B-drive inhibition
BlankMode I 2C HlockEn I2C H-lock detector
L1=No blank/blank level L2=H-lock/unlock level
HLckVbk 3 L3=L1+L2
V-sawtooth discharge V-sync
R S
Q
I2C I2C bit
Int. signal
3 Pin
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9.8.4 Composite output HLckVBk The composite output HLckVBk provides, at the same time, information about lock state of PLL1 and early vertical blanking pulse. As both signals have two logical levels, a four level signal is used to define the combination of the two. Schematic diagram putting together all safety functions and composite PLL1 lock and V-blanking indication is in Figure 15, the combinations, their respective levels and the HLckVBk configuration in Figure 16. The early vertical blanking pulse is obtained by a logic combination of vertical synchronization pulse and pulse corresponding to vertical oscillator discharge. The combination corresponds to the drawing in Figure 16. The blanking pulse is started with Figure 16. Levels on HLckVBk composite output
the leading edge of any of the two signals, whichever comes first. The blanking pulse is ended with the trailing edge of vertical oscillator discharge pulse. The device has no information about the vertical retrace time. Therefore, it does not cover, by the blanking pulse, the whole vertical retrace period. By means of BlankMode I2C bus bit, when at 1 (default), the blanking level (one of two according to PLL1 status) is made available on the HLckVBk permanently. The permanent blanking, irrespective of the BlankMode I2C bus bit, is also provided if the supply voltage is low (under VCCEn or VCCDis thresholds), if the X-ray protection is active or if the V-drive signal is disabled by VOutEn I2C bus bit.
VCC
L1 - No blank/blank level L2 - H-lock/unlock level
3 HLckVBk L1(L)+L2(H) ISinkLckBlk
L1(H)+L2(H)
V OLckBlk L1(L)+L2(L)
L1(H)+L2(L)
V-early blanking HPLL1 locked
No Yes
Yes Yes
No No
Yes No
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Figure 17. Ground layout recommendations
32 1 2 TDA9115 31 30 3 29 4 28 5 27 6 26 7 8 25 24 9 23 10 11 22 21 12 20 13 19 14 18 15 16 17
General Ground
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10 - INTERNAL SCHEMATICS
Figure 18. Figure 21.
12V 5V RefOut 13
5
Pins 1-2 H/HVSyn VSyn 200 HPLL2C
Figure 19.
12V 13 RefOut
Figure 22.
12V RefOut 13
HLckVBkl 3
C0 6
Figure 20.
Figure 23.
12V 12V Pin 13 RefOut 13
R0 8 HOSCF Pin 4
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Figure 24.
Figure 27.
HPLL1F 9
12V
HFly 12
Figure 25.
Figure 28.
12V RefOut
HPosF 10 BComp 14
Figure 26.
12V 5V 5V
Figure 29.
12V
BRegIn 15 HMoire 11
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Figure 30.
Figure 33.
12V 12V
BISense16
VAGCCap 20
Figure 31.
Figure 34.
12V
12V
VCap 22
18 VEHTIn 17 HEHTIn
Figure 32.
Figure 35.
12V
Pin 13 12V
VOSCF
19
VOut 23
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Figure 36.
12V
Figure 39.
24 EWOut
32 VDyCor
30 SCL 31SDA
Figure 37.
12V
XRay
25
Figure 38.
12V
26 HOut 28 BOut
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11 - PACKAGE MECHANICAL DATA
32 PINS - PLASTIC SHRINK
E E1 A2
A1
A
C L B B1 e Stand-off eA eB D 32 17 1 16 Millimeters Min. 3.556 0.508 3.048 0.356 0.762 .203 27.43 9.906 7.620 3.556 0.457 1.016 0.254 27.94 10.41 8.890 1.778 10.16 12.70 2.540 3.048 3.810 0.100 0.120 4.572 0.584 1.397 0.356 28.45 11.05 9.398 Typ. 3.759 Max. 5.080 Min. 0.140 0.020 0.120 0.014 0.030 0.008 1.080 0.390 0.300 0.140 0.018 0.040 0.010 1.100 0.410 0.350 0.070 0.400 0.500 0.150 0.180 0.023 0.055 0.014 1.120 0.435 0.370
Dimensions A A1 A2 B B1 C D E E1 e eA eB L
Inches Typ. 0.148 Max. 0.200
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12 - GLOSSARY
AC ACK AGC COMP CRT DC EHT EW H/W HOT I2C IIC MCU NAND NPN OSC PLL PNP REF RS, R-S S/W TTL VCO Alternate Current ACKnowledge bit of I2C-bus transfer Automatic Gain Control COMParator Cathode Ray Tube Direct Current Extra High Voltage East-West HardWare Horizontal Output Transistor Inter-Integrated Circuit Inter-Integrated Circuit Micro-Controller Unit Negated AND (logic operation) Negative-Positive-Negative OSCillator Phase-Locked Loop Positive-Negative-Positive REFerence Reset-Set SoftWare Transistor Transistor Logic Voltage-Controlled Oscillator
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Revision follow-up
PRODUCT PREVIEW
June 2000 version 2.0 Document created (issued from TDA9112) Work on figures and text; version finalized and displayed on Intranet. July 2000 version 2.1 Sentence modified in first page : The internal sync processor.;." replaced by :"the device only requires..;" Bloc diagram : addition of Hsize under E/W correction Quick Reference Data: Addition of parrallelogram Register Map: subaddress 08: 0:No tracking Few corrections in text.
PRELIMINARY DATA
September 2000 version 3:0 Uniformity in the writing of cross references for notes. In internal schematics, correction of figure for pin 11. In bloc diagram: the line between PLL2 and HMoire controller has been deleted In Horizontal Moire Cancellation: 1 sentence changed VDC AMP replaced by VDC-AMP In electrical parameters: VHMoire becomes VAC-HMoire Addition of VDC-HMoire,. January 11, 2001 version 3.1 page 6: value for autosync frequency ratio replaced : 4.28 instead of 4.5 previously. April 19, 2001 page 16 version 3.2 Section 6.9 .Vtrh-XRay: new values 7.65 min, 7.9 typ., 8.2 max.
DATASHEET
July 18, 2001 version 4.0 Section 9.4.1 right column"The higher its value,..." ---> "The lower its value" Section 9.5 ."...at the vertical middle..." ---> "...in the vertical middle..." Section 6.6 : addition of [fmax] to parameter "VEW/VEW[fmax].VHO" .and changed its value to 20 Note 28: added: "VEW[fmax] is the value at condition VHO>VHOThrfr". Section 6.4 : addition of min and max values for VHPosF and VTopHPLL2C Section 6.5 addition of min and max values for VVOB + correction of typ. value
2
Section 6.8 addition of min and max values for VThrBlsCurr and VBReg, max value added for VBOSat Section 6.9 addition of min and max values for VHPos Section 9.4 "stabilizing time" changed to "stabilization time" (twice) Section 6.9 : max values for vertical moire cancellers moved to typ. values
TDA9115
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this public ation are subject to change without notice. This publicati on supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems witho ut the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2001 STMicroelectronics - All Rights Reserved. Purchase of I C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A.
2
http:// www.st.com
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